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IDT74ALVCH162821 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
FEATURES:
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH162821
DESCRIPTION:
This 20-bit bus-interface flip-flop is built using advanced CMOS technology. The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH162821 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The ALVCH162821 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
* Balanced Output Drivers: 12mA * Low switching noise
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1O E
1
2O E
28
1C LK
56
2C LK
29
C1
1D 1 55 1D
2
C1
1Q 1
2D 1 42 1D
15
2Q 1
One of 10 Channels
One of 10 Channels
TO 9 OTHER CHAN NELS
TO 9 OTHER CHAN NELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4538/1
IDT74ALVCH162821 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1O E 1Q 1 1Q 2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100 Unit V V C mA mA mA mA
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1C LK 1D 1 1D 2
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
1Q 3 1Q 4
GND
1D 3 1D 4
VCC
1Q 5 1Q 6 1Q 7
VCC
1D 5 1D 6 1D 7
GND
1Q 8 1Q 9 1Q 10 2Q 1 2Q 2 2Q 3
GND
1D 8 1D 9 1D 10 2D 1 2D 2 2D 3
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
GND
2Q 4 2Q 5 2Q 6
GND
2D 4 2D 5 2D 6
PIN DESCRIPTION
Pin Names xDx xCLK xQx xOE Data Inputs
(1)
Description Clock Input 3-State Outputs 3-State Output Enable Inputs (Active LOW)
VCC
2Q 7 2Q 8
VCC
2D 7 2D 8
GND
2Q 9 2Q 10 2O E
GND
2D 9 2D 10 2C LK
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH 10-BIT FLIP-FLOP)(1)
Inputs xOE xCLK H or L X xDx H L X X L L L H Output xQx H L Q0(2) Z
SSOP/ TSSOP/ TVSOP TOP VIEW
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established.
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IDT74ALVCH162821 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH162821 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance per Flip Flop Outputs enabled Power Dissipation Capacitance per Flip Flop Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 40 26 VCC = 3.3V 0.3V Typical 45 28 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(O) Propagation Delay xCLK to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Set-up Time, data before xCLK Hold Time, data after xCLK Pulse Duration, xCLK HIGH or LOW Output Skew(2) 4.7 0 3.3 -- -- -- -- -- 4.1 0 3.3 -- -- -- -- -- 3.6 0 3.3 -- -- -- -- 500 ns ns ns ps 1 6.2 -- 5.5 1 5.1 ns 1 7 -- 6.6 1 5.5 ns Parameter Min. 150 1 Max. -- 6.3 VCC = 2.7V Min. 150 -- Max. -- 5.8 VCC = 3.3V 0.3V Min. 150 1 Max. -- 5 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH162821 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
SAME PHASE INPUT TRANSITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T.
VOUT
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
Enable and Disable Times
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. VIH DATA VT INPUT 0V tSU tH VIH TIMING VT INPUT 0V tREM VIH ASYNCHRONOUS VT CONTROL 0V VIH SYNCHRONOUS VT CONTROL tSU 0V tH
ALVC Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH INPUT VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2
ALVC Link
Set-up, Hold, and Release Times
tPLH1
tPHL1
LOW-HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
VT
tSK (x)
tSK (x)
VT VOL
VT
ALVC Link
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH162821 3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX ALVC X XX Fam ily XXX Device Type XX Package Tem p. R ange Bus-Hold
PV PA PF 821 162
Shrink S m all Outline P ackage Thin Shrink Small Outline Package Thin Very Sm all Outline Package 20-Bit Bus-Interface Flip-Flop with 3-State Outputs Double-Density with Resistors, 12mA
H 74
Bus-Hold -40C to +85C
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